1. Field of the Invention
The present invention relates generally to a microprocessor and, more particularly, to a bus interface unit which can simultaneously proceed with two bus cycles as one among internal units in a high-performance microprocessor.
2. Description of the Prior Art
With the improvement of the microprocessor's performance caused by the development of semiconductor design and fabrication techniques, an internal core unit has been rapidly developed. However, peripheral units communicating with the internal core through a bus have been developed relatively slow due to their inherent specialty (since the speed of a semiconductor memory is much slower than that of a microprocessor, a great loss of cycle is produced even by one access of the memory though the internal execution is proceeding very quickly.). Accordingly, the importance of the bus interface unit for interfacing them has been extended. Specifically, in case of a microprocessor adopting a superscalar type wherein a plurality of execution units are provided so as to simultaneously execute a plurality of instructions, or adopting a super-pipeline type wherein a typical pipeline is subdivided, a large number of bus activities are required in comparison to a conventional microprocessor, and thus it is required to simultaneously process requests of respective bus cycles which are requested from respective pipelines during one cycle.
As a result, in order to satisfy the speed difference between the internal core and the peripheral units and the necessity of plentiful bus operations required in the superscalar structure, the bus interface unit which is an interface block between them should be improved.